1. Field of the Invention
The present invention relates to a carbon-doped silicon oxide film and a damascene structure using the same, and in particular, to a low-carbon-doped silicon oxide film formed with a redox gas, and a damascene structure using dual hard films constituted by the low-carbon-doped silicon oxide.
2. Description of the Related Art
Integrated circuits have evolved into complicated devices that include various components. (e.g., SRAM (static random access memory) transistor, MIM (metal insulator metal), RFIC (radio frequency integrated circuit) and logic circuits on a single chip. The evolution of chip designs demands a continuous improvement on circuit speed and reliability. Hence, this give rises to a need to compact the devices into higher packing density to achieve faster transistor speed. Nevertheless, down sizing of the devices is not always preferable for chipmakers. Increasing in density up to the sub atomic level will cause RC (resistance capacitance) delay, which degrades the transistor performance. Therefore, this necessitates the use of low dielectric constant inter-metallic dielectric films to replace the conventional silicone oxide films.
A material that may be considered suitable for such a task is a carbon-doped silicon dioxide film. Using this material to divide a metal line may yield a device having reduced propagation delay, cross-talk noise and power dissipation. Although this film is seems to be perfect for replacing silicon dioxide films, there are other film properties that may not be comparable to silicon dioxide films. For instance, replacing a silicon dioxide film may cause adverse effects on other integration modules. One inevitable long-standing problem is etching of the carbon-doped silicon oxide film. The etching profiles will deviate due to excessive carbon by-products releasing from the film. Furthermore, the excess carbons arise from the film will interfere with etching and stop it prior to reaching a desired depth, increasing a possibility of incomplete etching in via chains. Incomplete etching will be a cause of an open circuit in a copper line. On top of this problem, the carbon content can also cause excessive micro loading (i.e., difference in etch rate between an isolated trench and a dense trench) which is impossible to be adjusted by an etching process. In general, a high carbon content in a film is not desirable except for reducing its κ value. Accordingly, the carbon level in the film needs to be controlled to an acceptable level.
On top of these problems, stress migration has become a dominant problem in smaller size wire lines. This occurs using weaker IMD films in place of the conventional oxide films. New developments of integration methodology are required to improve this variable so that low κ films can coexist with copper wires. Hence, the present invention concerns the use of dual hard layers each disposed at bottoms of vias prior to an IMD film to enhance copper wire reliability.
Various damascene methods have been disclosed in the art of microelectronic fabrication for forming within microelectronic fabrications damascene structures with desirable properties.
Damascene methods include, but are not limited to, damascene methods disclosed in: (1) U.S. Pat. No. 6,100,184 to Zhao et al., wherein a dual damascene method for forming a copper-containing contiguous-patterned conductor interconnect and a patterned conductor stud layer within a corresponding trench contiguous with a corresponding via formed through a dielectric layer formed of a comparatively low dielectric constant material to contact a copper-containing conductor layer formed thereunder, while employing a conductor barrier/etch stop layer formed selectively passivating only the top surface of the copper-containing conductor layer formed thereunder; (2) U.S. Pat. No. 6,140,226 to Grill et al., wherein a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed of a comparatively low dielectric constant dielectric material while employing a sidewall liner layer for purposes of protecting from lateral etching a sidewall of the trench when forming contiguous therewith the via while employing the dual damascene method; (3) U.S. Pat. No. 6,177,364 to Huang, wherein a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed of a comparatively low dielectric constant fluorosilicate glass (FSG) dielectric material while employing a hydrogen-nitrogen plasma treatment for purposes of passivating a sidewall surface of the dielectric layer within the corresponding trench contiguous with the corresponding via prior to forming therein the contiguous patterned conductor interconnect and patterned conductor stud layer; and (4) U.S. Pat. No. 6,211,092 to Tang et al., wherein a counterbore type dielectric etch method which may be employed when forming through a dielectric layer a dual damascene aperture employed within a dual damascene method, wherein the counterbore type dielectric etch method employs a plurality of etch steps when first forming a via through the dielectric layer.
Desirable in the art of microelectronic fabrication are additional damascene processes and materials which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers formed interposed between patterned microelectronic dielectric layers formed of comparatively low dielectric constant materials, resulting in attenuated damage to the microelectronic dielectric layers.
This is true for all low dielectric constant films that are currently available on the market. These films have an Elastic modulus of lower than 10 GPa measured with a MTS Nano-indenter. Hence, this required a new approach to strengthen the dual damascene structure.
To further explain the application of such films, conventional integration methods will be described below. In implementing conventional dual damascene techniques wherein a via is formed before forming a trench, an etch stop layer is formed on and below a first dielectric layer and serves as an overlaying capped metal layer. The etch stop layer are typically formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, and is chosen for its high etch selectivity with respect to an overlying second dielectric layer which is then deposited on the etch stop layer. A photoresist mask is then formed over the second dielectric layer, and anisotropic etching is conducted to form a via through the first and second dielectric layers and stopped on the bottom etch stop layer. Subsequently, a trench pattern is formed on the second dielectric layer with Barc (Barrier Anti Reflective Coating) filling the via (Planarization Barc Fill). Trench anisotropic etching with a photoresist is conducted to form the trench and stopped on the intermediate etch stop layer. Finally, the photoresist is removed with conventional ashing process, and Copper metallization is commenced.
With reference to U.S. Pat. No. 6,531,398B1, which states the art of using an organosilicate film to reduce capacitive coupling between metal interconnects to be formed in a damascene structure, the κ of the film is below 3.0. However, the above invention makes use of a low carbon film as a cap layer with an option as an IMD but its κ is above 3.0. The purpose of the film is somewhat different in terms of application. The usage of such a layer is to protect the underlying film from CMP damages and optionally protect the etch profile (Etch recipe tuning is required). Furthermore, the above invention requires a hard layer preferably SiC, and a low carbon hard film to form at the bottom of a via. Generally, the above invention's approaches are based on a physical, rather than an electrical, process integration point of view.
As miniaturization proceeds apace with an attendant shrinkage in size of metal lines, e.g., metal lines having a width of about 0.25 micron or less, e.g., about 0.1 micron or less, the ILD (interlayer dielectric) dielectric constant increasingly becomes more important, including the dielectric constant of an etch stop layer. Accordingly, there is a need for interconnection methodology enabling the formation of metal features, such as metal lines, with high dimensional accuracy and low effective κ-value.